1. Field of the invention
The present invention relates to an interface circuit and a clock output method for the interface circuit.
2. Description of the Related Art
Apparatus sets such as car audio and home audio have a plurality of data processing circuits for data processing associated with audio incorporated therein. These data processing circuits are connected in parallel via a controller such as a microcomputer and buses as needed, and by the controller supplying data, each of them executes data processing synchronously with data processing being executed by the other data processing circuits.
With reference to FIG. 9, a data processing system comprising a plurality of data processing circuits and a controller will be described. FIG. 9 is a block diagram for explaining a data processing system comprising a plurality of data processing circuits and a controller. The plurality of data processing circuits include, but not limited to, a PLL (Phase Locked Loop), an LCD (Liquid Crystal Display) driver, a DSP (Digital Signal Processor), an FM multiple receive circuit.
The PLL 4, LCD driver 6, DSP 8, and FM multiple receive circuit 10 are connected to the controller 2 via a data bus DB1 for transmitting a control signal CE, a data bus DB2 for transmitting a clock signal CL (or clock CL), a data bus DB3 for transmitting data DI, and a data bus DB3 for transmitting data D0 as needed.
The controller 2 outputs control signal CL, clock CL, and data DI to the PLL 4, LCD driver 6, DSP 8, and FM multiple receive circuit 10. Also, the controller 2 has data D0 from the PLL 4, LCD driver 6, DSP 8, or FM multiple receive circuit 10 inputted therein while outputting control signal CE and clock CL. The PLL 4, LCD driver 6, DSP 8, or FM multiple receive circuit 10 may not be connected to the controller 2 via data bus DB4. In this embodiment, for example, the controller 2 and the LCD driver 6 are not connected via data bus DB4.
The PLL 4 is for executing tuning of an electronic tuner, and has an interface circuit 4A that performs data input/output with the controller 2 and a data register 4B that holds data output from the interface circuit 4A. The LCD driver 6 is for executing frequency display processing for the electronic tuner, and has an interface circuit 6A that receives data input from the controller 2 and a data register 6B that holds data output from the interface circuit 6A. The DSP 8 is for executing digital processing on audio data, for example, and has an interface circuit 8A that performs data input/output with the controller 2 and a data register 8B that holds data output from the interface circuit 8A. The FM multiple receive circuit 10 is for decoding. FM-multiple, multiple, superposed data, and has an interface circuit 10A that performs data input/output with the controller 2 and a data register 10B that holds data output from the interface circuit 10A.
===Example of the Interface Circuit===
With reference to FIGS. 9, 10, and 11, an example of the interface circuit used in the PLL 4, LCD driver 6, DSP 8, and FM multiple receive circuit 10 of FIG. 9 will be described. FIG. 10 is a circuit diagram showing an example of the interface circuit. FIG. 11 is a time chart for explaining the operation of the interface circuit of FIG. 10. Note that the interface circuit of FIG. 10 does not have data bus DB4 for outputting data D0 to the controller 2.
The interface circuit has control signal CE, clock CL, and data DI inputted therein, and outputs clock SCL and data SDI. The interface circuit comprises an AND gate 102 and an AND gate 104 (clock output circuit). The AND gate 102 outputs data DI as data SDI depending on the level of control signal CE. That is, the AND gate 102 closes when control signal CE is at “L” (low level), and opens and outputs data DI as data SDI when control signal CE is at “H” (high level). The AND gate 104 outputs clock CL as clock SCL depending on the level of control signal CE. That is, when control signal CE is at “L”, the AND gate 104 closes and, when control signal CE is at “H”, opens and outputs clock CL as clock SCL.
The controller 2 holds clock CL at “L” and lets data DI be indefinite when control signal CE is at “L”. The controller 2 outputs clock CL and data DI synchronous with the clock CL when control signal CE is at “H”. That is, when control signal CE is at “L”, the AND gate 102 outputs data SDI of “L” and the AND gate 104 outputs clock SCL of “L”. When control signal CE is at “H”, the AND gate 102 outputs data SDI that is the same as data DI and the AND gate 104 outputs clock SCL that is the same as clock CL. By this means, the data register serially reads in data SDI synchronously with clock SCL and holds the data. The data processing circuit performs required data processing on the bit value held in the data register. Note that when outputting clock CL and data DI, the controller 2 has to enable a data processing circuit as a target and disable the other data processing circuits, which are not a target. Hence, the program processing load of the controller 2 itself is large.
===Another Example of the Interface Circuit===
With reference to FIGS. 9, 13, and 14, another example of the interface circuit used in the PLL 4, LCD driver 6, DSP 8, and FM multiple receive circuit 10 of FIG. 9 will be described. FIG. 13 is a circuit diagram showing another example of the interface circuit. FIG. 14 is a time chart for explaining the operation of the interface circuit of FIG. 13. Note that the interface circuit of FIG. 13 does not have data bus DB4 for outputting data DO to the controller 2. The interface circuit of FIG. 13 identifies a data processing circuit as a target with hardware, thereby reducing the program processing load of the controller 2 itself.
The PLL 4, LCD driver 6, DSP 8, and FM multiple receive circuit 10 have respective intrinsic address codes to identify them. When control signal CE is at “L”, the controller 2 outputs clock CL and data DI (address code A0 to A7) synchronous therewith, and when control signal CE is at “H”, the controller 2 outputs clock CL and data DI (data D0 to Dn−1) synchronous therewith and subsequent to data DI (address code A0 to A7). Note that when control signal CE is at “L”, the controller 2 holds clock CL at “L” except while data DI (address code A0 to A7) is output, and that the address code is not limited to an 8-bit code.
The interface circuit has control signal CE, clock CL, and data DI inputted therein, and outputs clock SCL and data SDI. The interface circuit comprises an address register 202, an address decoder 204, a delay circuit 206, an inverter 208, an AND gate 210, an OR gate 212, a D flip-flop 214, an AND gate 216, and an AND gate 218 (clock output circuit). The address register 202 serially reads in data DI (address code A0 to A7) at the rise timings of clock CL. The address decoder 204 checks whether the 8-bit address code A0 to A7 inputted in the address register 202 matches the intrinsic address code, and when both match, outputs “H”, for example. Note that the address decoder 204 is hardware including a PLA (Programmable Logic Array), logic gates and the like. The OR gate 212 outputs “L” only for the delay time of the delay circuit 206 after the change point of control signal CE from “H” to “L”. The AND gate 210 outputs “H” only for the delay time of the delay circuit 206 after the change point of control signal CE from “L” to “H”. By this means, the D flip-flop 214 is reset at the change point of control signal CE from “H” to “L”, and at the change point of control signal CE from “L” to “H”, reads in and holds the decode output of the address decoder 204 with outputting data EN, which is the same as the decode output. Specifically, when the 8-bit address code A0 to A7 inputted in the address register 202 matches the preset intrinsic address code assigned to the data processing circuit such as the PLL 4, LCD driver 6, DSP 8, or FM multiple receive circuit 10, the D flip-flop 214 outputs data EN of “H”. The AND gate 216 outputs data DI (data D0 to Dn−1) as data SDI depending on the level of data EN. That is, when data EN is at “L”, the AND gate 216 closes, and when data EN is at “H”, opens and outputs data DI (data D0 to Dn−1) as data SDI. The AND gate 218 outputs clock CL as clock SCL depending on the levels of control signal CE and data EN. That is, when either control signal CE or data EN is at “L”, the AND gate 218 closes, and when control signal CE and data EN are at “H”, opens and outputs clock CL as clock SCL.
When control signal CE is at “L”, data EN is also at “L”. Hence, the AND gate 216 outputs data SDI of “L”, and the AND gate 218 outputs clock SCL of “L”. When control signal CE is at “H”, data EN is also at “H”. Hence, the AND gate 216 outputs data SDI that is the same as data DI (data D) to DN−1), and the AND gate 218 outputs clock SCL that is the same as clock CL. By this means, the data register serially reads in data SDI synchronously with clock SCL and holds the data. The data processing circuit performs required data processing on the bit value held in the data register. The above is described, for example, in Japanese Patent Application Examined (KOKOKU) Publication No. Hei 3-31298.
According to the specification of controllers 2 themselves, when stopping clock CL, some controllers 2 hold clock CL at “L” while the others hold clock CL at “H”.
FIG. 11 is a time chart for explaining the operation of the interface circuit of FIG. 10 for the specification that the controller 2 holds clock CL at “L”. In contrast, FIG. 12 is a time chart for explaining the operation of the interface circuit of FIG. 10 for the specification that the controller 2 holds clock CL at “H”. For the latter specification that the controller 2 holds clock CL at “H”, the AND gate 104 outputs one clock (dummy clock) at a timing just before the AND gate 102 outputs data D0, and thereby the data register may read in data of “L” before data D0 and hold it, thus causing wrong data processing by the data processing circuit.
Furthermore, FIG. 14 is a time chart for explaining the operation of the interface circuit of FIG. 13 for the specification that the controller 2 holds clock CL at “L”. In contrast, FIG. 15 is a time chart for explaining the operation of the interface circuit of FIG. 13 for the specification that the controller 2 holds clock CL at “H”. For the latter specification that the controller 2 holds clock CL at “H”, the AND gate 216 outputs address code A7 just before data DO and the AND gate 218 outputs one clock (dummy clock) at a timing while the AND gate 216 outputs address code A7, and thereby the data register may read in address code A7, thus causing wrong data processing by the data processing circuit.
Moreover, even if the data processing circuit or the interface circuit is provided with a clock counter for counting the number of clocks of clock SCL, clocks of clock SCL that are the same in number as bits of data SDI may not be able to be output depending the specification of the controller 2, thus causing wrong data processing by the data processing circuit. Furthermore, even if the data processing circuit or the interface circuit is provided with a plurality of clock counters or a complex clock counter according to the specification of the controller 2, the problem occurs inevitably that the circuit scale becomes extremely large.